Epyc

Epyc (stylized as EPYC) is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets.

Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using the Infinity Fabric interconnect.

History

In March 2017, AMD announced plans to re-enter the server market with a platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May. That June AMD officially launched Epyc 7001 series processors, offering up to 32 cores per socket, and enabling performance that allowed Epyc to be competitive with the competing Intel Xeon Scalable product line. Two years later, in August 2019, the Epyc 7002 "Rome" series processors, based on the Zen 2 microarchitecture, launched, doubling the core count per socket to 64, and increasing per-core performance dramatically over the last generation architecture.

In March 2021, AMD launched the Epyc 7003 "Milan" series, based on the Zen 3 microarchitecture. Epyc Milan brought the same 64 cores as Epyc Rome, but with much higher per-core performance, with the Epyc 7763 beating the Epyc 7702 by up to 22 percent despite having the same number of cores and threads. A refresh of the Epyc 7003 "Milan" series with 3D V-Cache, named Milan-X, launched on March 21, 2022, using the same cores as Milan, but with an additional 512 MB of cache stacked onto the compute dies, bringing the total amount of cache per CPU to 768 MB.

In September 2021, Oak Ridge National Laboratory partnered with AMD and HPE Cray to build Frontier, a supercomputer with 9,472 Epyc 7453 CPUs and 37,888 Instinct MI250X GPUs, becoming operational by May 2022. As of November 2023, it is the most powerful supercomputer in the world according to the TOP500, with a peak performance of over 1.6 exaFLOPS.

In November 2021, AMD detailed the upcoming generations of Epyc, also unveiling the new LGA-6096 SP5 socket that would support the new generations of Epyc chips. Codenamed Genoa, the first Zen 4 based Epyc CPUs is built on TSMC's N5 node and supports up to 96 cores and 192 threads per socket, alongside 12 channels of DDR5, 128 PCIe 5.0 lanes, and Compute Express Link 1.1. AMD also shared information regarding the sister chip of Genoa, codenamed Bergamo. Bergamo is be based on a modified Zen 4 microarchitecture named Zen 4c, designed to allow for much higher core counts and efficiency at the cost of lower single-core performance, targeting cloud providers and workloads, compared to traditional high performance computing workloads. It is compatible with Socket SP5, and supports up to 128 cores and 256 threads per socket.

In November 2022, AMD launched their 4th generation Epyc lineup, codenamed Genoa. Some tech reviewers and customers had already received hardware for testing and benchmarking, and third party benchmarks of Genoa parts were immediately available. The flagship part, the 96 core Epyc 9654, set records for multi-core performance, and showed up to 4× performance compared to Intel's flagship part, the Xeon Platinum 8380. High memory bandwidth and extensive PCIe connectivity removed many bottlenecks, allowing all 96 cores to be utilized in workloads where previous generation Milan chips would have been I/O-bound. Genoa was also the first x86 server CPU to support CXL, allowing for further expansion of memory and other devices with a high bandwidth interface built on PCIe 5.0.

In June 2023, AMD began shipping the 3D-Vcache enabled Genoa-X lineup, a refresh of Genoa that uses the same 3D die stacking technology as Milan-X to enable up to 1152 MB of L3 cache, a 50% increase over Milan-X, which had a maximum of 768 MB of L3 cache. On the same day, AMD also announced the release of their cloud optimized Zen 4c SKUs, codenamed Bergamo, offering up to 128 cores per socket, utilizing a modified version of the Zen 4 core that was optimized for power efficiency and to reduce die space. Zen 4c cores do not have any instructions removed compared to standard Zen 4 cores, instead, the amount of cache per core is reduced from 4 MB to 2 MB, and the frequency of the cores is reduced. Bergamo is socket compatible with Genoa, using the same SP5 socket and supporting the same CXL, PCIe, and DDR5 capacity as Genoa.

In September 2023, AMD launched their low power and embedded 8004 series of CPUs, codenamed Siena. Siena utilizes a new socket, called SP6, which has a smaller footprint and pin count than the SP5 socket of its contemporary Genoa processors. Siena utilizes the same Zen 4c core architecture as Bergamo cloud native processors, allowing up to 64 cores per processor, and the same 6 nm I/O die as Bergamo and Genoa, although certain features have been cut down, such as reducing the memory support from 12 channels of DDR5 to only 6, and removing dual socket support.

AMD Epyc CPU codenames follow the naming scheme of Italian cities, including Milan, Rome, Naples, Genoa, Bergamo, Siena, and Turin.

Design

Epyc CPUs use a multi-chip module design to enable higher yields for a CPU than traditional monolithic dies. First generation Epyc CPUs are composed of four 14 nm compute dies, each with up to 8 cores. Cores are symmetrically disabled on dies to create lower binned products with fewer cores but the same I/O and memory footprint. Second and Third gen Epyc CPUs are composed of eight compute dies built on a 7 nm process node, and a large input/output (I/O) die built on a 14 nm process node. Third gen Milan-X CPUs use advanced through-silicon-vias to stack an additional die on top of each of the 8 compute dies, adding 64 MB of L3 cache per die.

Epyc CPUs supports both single socket and dual socket operation. In a dual socket configuration, 64 PCIe lanes from each CPU are allocated to AMD's proprietary Infinity Fabric interconnect to allow for full bandwidth between both CPUs. Thus, a dual socket configuration has the same number of usable PCIe lanes as a single socket configuration. First generation Epyc CPUs had 128 PCIe 3.0 lanes, while second and third generation had 128 PCIe 4.0 lanes. All current Epyc CPUs are equipped with up to eight channels of DDR4 at varying speeds, though next gen Genoa CPUs are confirmed by AMD to support up to twelve channels of DDR5.

Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding Socket AM1), Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers, etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some features may require the use of additional controller chips to utilize.

Reception

Initial reception to Epyc was generally positive. Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency. In 2021 Meta Platforms selected Epyc chips for its metaverse data centers.

Epyc Genoa was well received, as it offered improved performance and efficiency compared to previous offerings, though received some criticism for not having 2 DIMMs per channel configurations validating, with some reviewers calling it an "incomplete platform".

List of Epyc processors

Server

First generation Epyc (Naples)

The following table lists the devices using the first generation design.

A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 PCIe lanes from each processor for the communication between processors.

Common features of EPYC 7001 series CPUs:

• Socket: SP3.
• All the CPUs support ECC DDR4-2666 in octa-channel mode (7251 supports only DDR4-2400).
• L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 128 PCIe 3.0 lanes.
• Fabrication process: GlobalFoundries 14LP.

Second generation Epyc (Rome)

In November 2018, AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors codenamed "Rome" and based on the Zen 2 microarchitecture. The processors feature up to eight 7 nm-based "chiplet" processors with a 14 nm-based IO chip providing 128 PCIe 4.0 lanes in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket. The 7 nm "Rome" is manufactured by TSMC. It was released on August 7, 2019. It has 39.5 billion transistors.

In April 2020, AMD launched three new SKUs using Epyc’s 7nm Rome platform. The three processors introduced were the eight-core Epyc 7F32, the 16-core 7F52 and the 24-core 7F72, featuring base clocks up to 3.7 GHz (up to 3.9 GHz with boost) within a TDP range of 180 to 240 watts. The launch was supported by Dell EMC, Hewlett Packard Enterprise, Lenovo, Supermicro, and Nutanix.

Common features of these CPUs:

• Codenamed "Rome"
• Zen 2 microarchitecture
• TSMC 7 nm process
• SP3 Socket
• 128 PCIe lanes
• Memory support: eight-channel DDR4-3200

Third generation Epyc (Milan)

At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture. Milan chips will use Socket SP3, with up to 64 cores on package, and support eight-channel DDR4 RAM and 128 PCIe 4.0 lanes. It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.

Milan CPUs were launched by AMD on March 15, 2021.

Milan-X CPUs were launched March 21, 2022. They use 3D V-Cache technology to increase the maximum L3 cache per socket capacity from 256 MB to 768 MB.

Fourth generation Epyc (Genoa, Bergamo and Siena)

On November 10, 2022, AMD launched the fourth generation of Epyc server and data center processors based on the Zen 4 microarchitecture, codenamed Genoa. At their launch event, AMD announced that Microsoft and Google would be some of Genoa's customers. Genoa features between 16 and 96 cores with support for PCIe 5.0 and DDR5. There was also an emphasis by AMD on Genoa's energy efficiency, which according to AMD CEO Lisa Su, means "lower total cost of ownership" for enterprise and cloud datacenter clients. Genoa uses AMD's new SP5 (LGA 6096) socket.

On June 13, 2023, AMD introduced Genoa-X with 3D V-Cache technology for technical computing performance and Bergamo (9734, 9754 and 9754S) for cloud native computing.

On September 18, 2023, AMD introduced the low power Siena lineup of processors, based on the Zen 4c microarchitecture. Siena supports up to 64 cores on the new SP6 socket, which is currently only used by Siena processors. Siena uses the same I/O die as Bergamo, however certain features, such as dual socket support, are removed, and other features are reduced, such as the change from 12 channel memory support to 6 channel memory support.

Embedded

First generation Epyc (Snowy Owl)

In February 2018, AMD also announced the Epyc 3000 series of embedded Zen CPUs.

Common features of EPYC Embedded 3000 series CPUs:

• Socket: SP4 (31xx and 32xx models use SP4r2 package).
• All the CPUs support ECC DDR4-2666 in dual-channel mode (3201 supports only DDR4-2133), while 33xx and 34xx models support quad-channel mode.
• L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 32 PCIe 3.0 lanes per CCD (max 64 lanes).
• Fabrication process: GlobalFoundries 14 nm.

Chinese variants

A variant created for the Chinese server market by Hygon Information Technology is the Hygon Dhyana system on a chip. It is noted to be a variant of the AMD Epyc, and is so similar that "there is little to no differentiation between the chips". It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market". Later Benchmarks showed that certain floating point instructions are performing worse, probably to comply with US export restrictions. AES and other western cryptography algorithms are replaced by Chinese variants throughout the design.

References

1. Zen (first generation)
2. Zen (microarchitecture)
3. List of AMD processors
4. Zen 4
5. Socket SP6
6. Zen 2
7. Zen 5
8. Socket SP5
9. Supermicro
10. Frontier (supercomputer)
11. Zen 3
12. Multi-channel memory architecture
13. DDR5 SDRAM
14. LUMI
15. Table of AMD processors
16. Socket SP3
17. Rome (disambiguation)
18. Ubuntu
19. AMD Optimizing C/C++ Compiler
20. Ryzen