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Zen 3

Zen 3 is the codename for a CPU microarchitecture by AMD, released on November 5, 2020. It is the successor to Zen 2 and uses TSMC's 7 nm process for the chiplets and GlobalFoundries's 14 nm process for the I/O die on the server chips and 12 nm for desktop chips. Zen 3 powers Ryzen 5000 mainstream desktop processors (codenamed "Vermeer") and Epyc server processors (codenamed "Milan"). Zen 3 is supported on motherboards with 500 series chipsets; 400 series boards also saw support on select B450 / X470 motherboards with certain BIOSes. Zen 3 is the last microarchitecture before AMD switched to DDR5 memory and new sockets, which are AM5 for the desktop "Ryzen" chips alongside SP5 and SP6 for the EPYC server platform and sTRX8. According to AMD, Zen 3 has a 19% higher instructions per cycle (IPC) on average than Zen 2.

On April 1, 2022, AMD released the new Ryzen 6000 series for the laptop, using an improved Zen 3+ architecture. On April 20, 2022, AMD also released the Ryzen 7 5800X3D desktop processor, which increases the single threading performance by another 15% in gaming by using, for the first time in a PC product, 3D vertically stacked L3 cache.

Features

Zen 3 is a significant incremental improvement over its predecessors, with an IPC increase of 19%, and being capable of reaching higher clock speeds.

Like Zen 2, Zen 3 is composed of up to 2 core complex dies (CCD) along with a separate IO die containing the I/O components. A Zen 3 CCD is composed of a single core complex (CCX) containing 8 CPU cores and 32 MB of shared L3 cache, this is in contrast to Zen 2 where each CCD is composed of 2 CCX, each containing 4 cores paired with 16 MB of L3 cache. The new configuration allows all 8 cores of the CCX to directly communicate with each other and the L3 Cache instead of having to use the IO die through the Infinity Fabric.

Zen 3 (along with AMD's RDNA2 GPUs) also implemented Resizable BAR, an optional feature introduced in PCIe 2.0, that was branded as Smart Access Memory (SAM). This technology allows CPU to directly access all of compatible video card's VRAM. Intel and Nvidia have since implemented this feature as well.

In Zen 3, a single 32MB L3 cache pool is shared among all 8 cores in a chiplet, vs. Zen 2's two 16MB pools each shared among 4 cores in a core complex, of which there were two per chiplet. This new arrangement improves the cache hit rate as well as performance in situations that require cache data to be exchanged among cores, but increases cache latency from 39 cycles in Zen 2 to 46 clock cycles and halves per-core cache bandwidth, although both problems are partially mitigated by higher clock speeds. Total cache bandwidth on all 8 cores combined remains the same due to power consumption concerns. L2 cache capacity and latency remain the same at 512KB and 12 cycles. All cache read and write operations are done at 32 bytes per cycle.

On April 20, 2022, AMD released the R7 5800X3D. It features, for the first time in a desktop PC product, 3D-stacked vertical L3 cache. Its extra 64 MB on top of the usual 32 MB increases the total amount to 96 MB and brings significant performance improvements for gaming, rivalling contemporary high-end consumer processors while being much more power efficient. It would later be followed by the 5600X3D and 5700X3D for lower-end market segments, and succeeded by the 7000X3D family of Zen 4 processors.

Improvements

Zen 3 has made the following improvements over Zen 2:

An increase of 19% in instructions per clock
The base core chiplet has a single eight-core complex (versus two four-core complexes in Zen 2)
A unified 32MB L3 cache pool equally available to all 8 cores in a chiplet, vs Zen 2's two 16MB pools each shared among 4 cores in a core complex.
- On mobile: A unified 16MB L3
A unified 8-core CCX (from 2x 4-core CCX per CCD)
Increased branch prediction bandwidth. L1 branch target buffer size increased to 1024 entries (vs 512 in Zen 2)
New instructions
- VAES – 256-bit Vector AES instructions
- INVLPGB – Broadcast TLB flushing
- CET_SS – Control-flow Enforcement Technology / Shadow Stack
Improved integer units
- 96 entry integer scheduler (up from 92)
- 192 entry physical register file (up from 180)
- 10 issue per cycle (up from 7)
- 256 entry reorder-buffer (up from 224)
- fewer cycles for DIV/IDIV ops (10...20 from 16...46)
Improved floating point units
- 6 μOP dispatch width (up from 4)
- FMA latency reduced by 1 cycle (down from 5 to 4)
Additional 64MB 3D vertically stacked dense library L3 cache (in -X3D models)

Feature tables

CPUs

APUs

APU features table

Products

On October 8, 2020, AMD announced four Zen 3-based desktop Ryzen processors, consisting of one Ryzen 5, one Ryzen 7, and two Ryzen 9 CPUs and featuring between 6 and 16 cores.

Desktop CPUs

The Ryzen 5000 series desktop CPUs are codenamed Vermeer. The models in the second table are based on Cezanne APUs with the integrated GPU disabled. Meanwhile the Ryzen Threadripper Pro 5000 series were codenamed Chagall.

Common features of Ryzen 5000 desktop CPUs:

Socket: AM4.
All the CPUs support DDR4-3200 in dual-channel mode.
L1 cache: 64 KB per core (32 KB data + 32 KB instruction).
L2 cache: 512 KB per core.
All the CPUs support 24 PCIe 4.0 lanes. 4 of the lanes are reserved as link to the chipset.
No integrated graphics.
Fabrication process: TSMC 7FF.

5100, 5500, and 5700 have no ECC support like non-Pro Ryzen 5000 Desktop APUs.

Common features of Ryzen 5000 (Cezanne) desktop CPUs:

Socket: AM4.
CPUs support DDR4-3200 in dual-channel mode.
L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
L2 cache: 512 KB per core.
CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
No integrated graphics.
Fabrication process: TSMC 7FF.

Common features of Ryzen 5000 workstation CPUs:

Socket: sWRX8.
All the CPUs support DDR4-3200 in octa-channel mode.
L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
L2 cache: 512 KB per core.
All the CPUs support 128 PCIe 4.0 lanes. 8 of the lanes are reserved as link to the chipset.
No integrated graphics.
Fabrication process: TSMC 7FF.

Desktop APUs

Cezanne

Common features of Ryzen 5000 desktop APUs:

Socket: AM4.
All the CPUs support DDR4-3200 in dual-channel mode.
L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
L2 cache: 512 KB per core.
All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
Includes integrated GCN 5th generation GPU.
Fabrication process: TSMC 7FF.

Mobile APUs

Cezanne

Barceló

Barceló-R

Common features of Ryzen 7030 notebook APUs:

Socket: FP6.
All the CPUs support DDR4-3200 or LPDDR4-4266 in dual-channel mode.
L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
L2 cache: 512 KB per core.
All the CPUs support 16 PCIe 3.0 lanes.
Includes integrated GCN 5th generation GPU.
Fabrication process: TSMC 7nm FinFET.

Embedded CPUs

Server CPUs

The Epyc server line of chips based on Zen 3 is named Milan and is the final generation of chips using the SP3 socket. Epyc Milan was released on March 15, 2021.

Zen 3+

Zen 3+ is the codename for a refresh of the Zen 3 microarchitecture, which focuses on power efficiency improvements. It was released in April 2022 with the Ryzen 6000 series of mobile processors.

Features and improvements

Zen 3+ has 50 new or enhanced power management features over Zen 3, and also provides an adaptive power management framework, as well as new deep sleep states. Altogether, this brings improvements to efficiency both during idle, and when under load, with up to 30% performance-per-watt increase over Zen 3, as well as longer battery life.

IPC is identical to that of Zen 3; the performance improvements of Ryzen 6000 over Ryzen 5000 mobile processors stem from it having a higher efficiency (hence more performance in power-constrained form factors like laptops), as well as the increased clock speeds from being built on the smaller TSMC N6 node.

The Rembrandt implementation of Zen 3+ also has support for DDR5 and LPDDR5 memory.

Products

Rembrandt

On April 1, 2022, AMD released the Ryzen 6000 series of mobile APUs, codenamed Rembrandt. It introduces PCIe 4.0 and DDR5/LPDDR5 for the first time in an APU for the laptop and also introduced RDNA2 integrated graphics to the PC. It is built on TSMC's 6 nm node.

Common features of Ryzen 6000 notebook APUs: